View UPD784916AGF_1332600.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
PD784915A, 784916A
16-BIT SINGLE-CHIP MICROCONTROLLERS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD784915A, 784916A are members of the NEC 78K/IV Series of microcontrollers equipped with a highspeed 16-bit CPU and are the successors of the 78K/I Series 8-bit single-chip microcontrollers for VCR software servo control. This series contains many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer unit) suitable for software servo control and VCR analog circuits. A one-time PROM version of the PD784916A, the PD78P4916, is also available. The functions of the PD784916A are described in detail in the following user's manuals. Be sure to read them before designing.
PD784915 Subseries User's Manual - Hardware: U10444E 78K/IV Series User's Manual - Instruction: U10905E
FEATURES
* High instruction execution speed realized by 16-bit CPU core * Minimum instruction execution time: 250 ns (with 8-MHz internal clock) * High internal memory capacity Part Number ROM 48 Kbytes 62 Kbytes RAM 1280 bytes
PD784915A PD784916A
* VCR analog circuits conforming to VHS Standard * CTL amplifier * RECCTL driver (rewritable) * CFG amplifier * DFG amplifier * DPG comparator * DPFG separation circuit (ternary separation circuit) * Reel FG comparator (2 channels) * CSYNC comparator * Timer unit (super timer unit) for servo control * Serial interface: 2 channels (3-wire serial I/O) * A/D converter: 12 channels (conversion time: 10 s) * Low-frequency oscillation mode: main system clock frequency = internal clock frequency * Low-power dissipation mode: CPU can operate with a subsystem clock. * Supply voltage range: VDD = 2.7 to 5.5 V * Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current
APPLICATIONS
Control system/servo/timer of VCR
Unless mentioned otherwise, the PD784916A is described as the representative product. The information in this document is subject to change without notice Document No. U11022EJ1V0DS00 (1st edition) Date Published July 1997 N Printed in Japan The mark shows major revised points.
(c)
1996
PD784915A, 784916A
ORDERING INFORMATION
Part Number Package 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm)
PD784915AGF-xxx-3BA PD784916AGF-xxx-3BA
Remark xxx indicates a ROM code number. Product Development of 78K/IV Series
: Under mass production : Under development
I2C bus supported
Multimaster I2C bus supported
PD784038Y
Standard
PD784225Y PD784225
80 pins, ROM correction was enhanced Multimaster I2C bus supported
PD784038 PD784026
Internal memory capacity was enhanced Pin compatible with PD784026 Multimaster I2C bus supported
Enhanced A/D, 16-bit timer, and power management
PD784216Y PD784216
100 pins, I/O and internal memory capacity was enhanced
PD784218Y PD784218
Internal memory capacity was enhanced ROM correction was added
PD784054 PD784046
ASSP On-chip 10-bit A/D
PD784908
On-chip IEBusTM Controller
PD78F4943
For CD-ROM, 56 Kbytes of flash memory
Multimaster I2C bus supported
PD784928Y PD784928
Function of the PD784915 was enhanced
PD784915
On-chip software servo control VCR analog circuit, enhanced timer
2
PD784915A, 784916A
Function List (1/2) Item Internal ROM capacity Internal RAM capacity Operating clock 48 Kbytes 1280 bytes 16 MHz (internal clock: 8 MHz) Low frequency oscillation mode: 8 MHz (internal clock: 8 MHz) Low power dissipation mode: 32.768 kHz (subsystem clock) Minimum instruction execution time I/O ports 54 Real-time output port Timer/counter input : 8 I/O : 46 11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation) Timer/counter TM0 (16 bits) TM1 (16 bits) FRC (22 bits) TM3 (16 bits) UDC (5 bits) EC (8 bits) EDV (8 bits) Capture register Input signal CFG DFG Super timer unit HSW VSYNC CTL TREEL SREEL VCR special circuit Compare register 3 3 2 1 4 1 Number of bits 22 22 16 22 16 22 22 Capture register 1 6 1 Measurable cycle 125 ns to 524 ms 125 ns to 524 ms 1 s to 65.5 ms 125 ns to 524 ms 1 s to 65.5 ms 125 ns to 524 ms 125 ns to 524 ms For HSW signal generation For CFG signal division Operating edge Remark 250 ns (with 8-MHz internal system clock)
PD784915A
64 Kbytes
PD784916A
* VSYNC separation circuit, HSYNC separation circuit * VISS detection, wide aspect detection circuits * Field identification circuit * Head amplifier switch/chroma rotation output circuit
General-purpose timer
Timer TM2 (16 bits) TM4 (16 bits) TM5 (16 bits)
Compare register 1 1 (capture/compare) 1
Capture register 1 -
PWM output Serial interface A/D converter
* 16-bit accuracy : 3 channels (carrier frequency: 62.5 kHz) * 8-bit accuracy : 3 channels (carrier frequency: 62.5 kHz) 3-wire serial I/O: 2 channels * BUSY/STRB control (1 channel only) 8-bit resolution x 12 channels, conversion time: 10 s
3
PD784915A, 784916A
Function List (2/2) Item Analog circuit
PD784915A
* CTL amplifier * RECCTL driver (rewritable) * DFG amplifier, DPG comparator, CFG amplifier * DPFG separation circuit (ternary separation circuit) * Reel FG comparator (2 channels) * CSYNC comparator
PD784916A
Interrupt External Internal Standby function
4 levels (programmable), vector interrupt, macro service, context switching 9 (including NMI) 19 (including software interrupt) HALT/STOP mode/low power dissipation mode/low power dissipation HALT mode STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/INTP2/KEY0-KEY4 pins
Watch function Supply voltage Package
0.5-second measurement, low-voltage operation (VDD = 2.7 V) VDD = 2.7 to 5.5 V 100-pin plastic QFP (14 x 20 mm)
4
PD784915A, 784916A
PIN CONFIGURATION (Top View)
* 100-pin plastic QFP (14 x 20 mm)
PD784915AGF-xxx-3BA PD784916AGF-xxx-3BA
CSYNCIN REEL0IN/INTP3 REEL1IN DFGIN DPGIN CFGCPIN CFGAMPO CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECCTLRECTTL+ CTLDLY AVSS2 ANI11 ANI10
P64 P65/HWIN P66/PWM4 P67/PWM5 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 PWM0 PWM1 SCK2 SO2 SI2/BUSY VDD XT1 XT2 VSS X2 X1 RESET IC PTO02 PTO01 PTO00 P87/PTO11 P86/PTO10 P85/PWM3 P84/PWM2 P83/ROTC P82/HASW 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ANI9 ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVDD2 P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI INTP0 INTP1 INTP2 P00 P01 P02 P03 P04 P05 P06
Caution
Directly connect the IC (Internally Connected) pins to VSS.
P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07
5
PD784915A, 784916A
ANI0-ANI11 AVDD1, AVDD2 AVSS1, AVSS2 AVREF BUSY BUZ CFGAMPO CFGCPIN CFGIN CLO CSYNCIN CTLDLY CTLIN DFGIN DPGIN ENV HASW HWIN IC INTP0-INTP3 KEY0-KEY4 NMI : Analog Input : Analog Power Supply : Analog Ground : Analog Reference Voltage : Serial Busy : Buzzer Output : Capstan FG Amplifier Output : Capstan FG Capacitor Input : Analog Unit Input : Clock Output : Analog Unit Input : Control Delay Input : CTL Amplifier Input Capacitor : Analog Unit Input : Analog Unit Input : Envelope Input : Head Amplifier Switch Output : Hardware Timer External Input : Internally Connected : Interrupt From Peripherals : Key Return : Nonmaskable Interrupt P00-P07 P40-P47 P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96 PTO00-PTO02 PTO10, PTO11 PWM0-PWM5 REEL0IN, REEL1IN RESET ROTC SCK1, SCK2 SI1, SI2 SO1, SO2 STRB VDD VREFC VSS X1, X2 XT1, XT2 : Pulse Width Modulation Output : Analog Unit Input : Reset : Chrominance Rotate Output : Serial Clock : Serial Input : Serial Output : Serial Strobe : Power Supply : Reference Amplifier Capacitor : Ground : Crystal (Main System Clock) : Crystal (Subsystem Clock) RECCTL+, RECCTL- : RECCTL Output/PBCLT Input : Port0 : Port4 : Port5 : Port6 : Port7 : Port8 : Port9 : Programmable Timer Output
CTLOUT1, CTLOUT2 : CTL Amplifier Output
6
PD784915A, 784916A
INTERNAL BLOCK DIAGRAM
NMI INTP0-INTP3
INTERRUPT CONTROL SYSTEM CONTROL
PWM0-PWM5 PTO00-PTO02 PTO10, PTO11 SUPER TIMER UNIT CLOCK OUTPUT BUZZER OUTPUT VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTLCTLDLY AVDD1, AVDD2 AVSS1, AVSS2 AVREF AN10-AN11
VDD VSS X1 X2 XT1 XT2 RESET CLO BUZ
KEY INPUT
KEY0-KEY4
P00-P07 78K/IV 16-bit CPU CORE (RAM: 512 bytes) REAL-TIME OUTPUT PORT P80, P82, P83 PORT0 ANALOG UNIT & A/D CONVERTER PORT4 PORT5 RAM 768 bytes ROM PORT6 PORT7 PORT8 PORT9 P00-P07 P40-P47 P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96
SI1 SO1 SCK1
SERIAL INTERFACE 1
SI2/BUSY SO2 SCK2 STRB
SERIAL INTERFACE 2
Remark Internal ROM capacity varies depending on the part number.
7
PD784915A, 784916A
SYSTEM CONFIGURATION EXAMPLE
* Camera-contained VCR
PD784916A
DFG DPG Drum motor M Driver DFGIN DPGIN PORT PWM0 PORT SCK1 SI1 SO1 INTP0 INTP0 SCK Cameracontrolling SO microcomputer SI PD784036 PORT PORT Key matrix
CFG
CFGIN
Capstan motor
M
Driver
PWM1 Camera block RECCTL+ PORT SCK2 SO2 BUSY CS CLK DATA BUSY
CTL head RECCTL-
LCD C/D
PD7225
Loading motor
M
Driver
PWM2 LCD display panel PORT
Audio/video signal processing circuit
Composite sync signal CSYNCIN Video head switch PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 Remote controller reception signal
PORT
STRB
CS CLK DATA BUSY STB
OSD
PD6461
Remote controller signal
INTP2 X1 X2 XT1
PORT XT2
Mechanical block
PC2800A
16 MHz
32.768 kHz
8
PD784915A, 784916A
* Stationary VCR
PD784916A
DFG DPG Drum motor M Driver DFGIN DPGIN PORT SCK1 SI1 SO1 STB CLK FIPTM C/D DOUT PD16311 DIN
PWM0
CFG
CFGIN FIP Key matrix
Capstan motor
M
Driver
PWM1 PORT SCK2 SO2 RECCTL+ CS CLK DATA OSD
PD6464
CTL head RECCTLPORT Composite sync signal Audio/video signal CSYNCIN Video head switch processing circuit PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 PWM5 PORT M Reel motor M Driver Reel FG1 PWM4 INTP2 REEL1IN Low frequency oscillation mode X1 X2 XT1 Remote controller reception signal Remote controller signal Driver PWM3 PORT Mechanical block
Loading motor
M
Driver
PWM2
Reel FG0
REEL0IN Tuner
PC2800A
XT2
8 MHz
32.768 kHz
9
PD784915A, 784916A
CONTENTS
1. DIFFERENCES AMONG PD784915 SUBSERIES PRODUCTS .................................................. 11 2. PIN FUNCTIONS .............................................................................................................................. 12
2.1 2.2 2.3 Port Pins ................................................................................................................................................ Pins Other Than Port Pins .................................................................................................................... I/O Circuits and Connection of Unused Pins ...................................................................................... 12 13 15
3. INTERNAL BLOCK FUNCTIONS .................................................................................................... 19
3.1 CPU Registers ....................................................................................................................................... 3.1.1 General-purpose registers ......................................................................................................... 3.1.2 Other CPU registers .................................................................................................................... Memory Space ....................................................................................................................................... Special Function Registers (SFRs) ..................................................................................................... Ports ....................................................................................................................................................... Real-time Output Port ........................................................................................................................... Super Timer Unit ................................................................................................................................... Serial Interface ...................................................................................................................................... A/D Converter ........................................................................................................................................ VCR Analog Circuits ............................................................................................................................. Watch Function ..................................................................................................................................... Clock Output Function ......................................................................................................................... 19 19 20 20 23 28 29 33 38 40 41 47 48
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11
4.
INTERNAL/EXTERNAL CONTROL FUNCTION ............................................................................ 49
4.1 Interrupt Function ................................................................................................................................. 4.1.1 Vector interrupt ........................................................................................................................... 4.1.2 Context switching ....................................................................................................................... 4.1.3 Macro service .............................................................................................................................. 4.1.4 Application example of macro service ..................................................................................... Standby Function .................................................................................................................................. Clock Generator Circuit ........................................................................................................................ Reset Function ...................................................................................................................................... 49 51 51 52 54 57 59 60
4.2 4.3 4.4
5. INSTRUCTION SETS ....................................................................................................................... 61 6. ELECTRICAL CHARACTERISTICS ............................................................................................... 65 7. PACKAGE DRAWING ..................................................................................................................... 77 8. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 78 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 79 APPENDIX B. RELATED DOCUMENTS ............................................................................................... 81
10
PD784915A, 784916A
1. DIFFERENCES AMONG PD784915 SUBSERIES PRODUCTS
The PD784915 subseries comprises the four products shown in Table 1-1. The PD784915A, which is a processshrinked version of the PD784915 is a low-cost product. The PD784916A is a version of the PD784915 with internal ROM extended to 62K bytes. The PD78P4916 is a product with the mask ROM of the PD784915, 784915A, and 784916A replaced by a writable one-time PROM. Therefore, it has the same functions as those of the PD784915, 784915A and 784916A, with only exception that it has PROM for internal ROM and a different capacity. Before using the PROM to perform debugging or preproduction of an application system and then using the mask ROM to proceed with volume production, etc., thoroughly check the differences between these products. For more information about the CPU functions and on-chip hardware, see PD784915 Subseries User's Manual - Hardware (U10444E). Table 1-1. Differences among PD784915 Subseries Products Item Internal ROM Internal RAM Internal memory capacity select register (IMS) Pin connections Other
PD784915, 784915A
Mask ROM 48K bytes 1280 bytes Not available pin functions.
PD784916A
Mask ROM 62K bytes 1280 bytes Not available
PD78P4916
One-time PROM 62K bytesNote 2048 bytesNote Available
The PD78P4916 has additional PROM write/read related Since these products are different in circuit scale and mask layout, they partly differ in noise resistance, noise radiation and electrical specifications.
Note
The internal PROM and internal RAM capacities can be changed by the internal memory capacity select register (IMS).
Caution
The PROM version and mask ROM version differ in noise immunity and noise radiation, etc. When considering replacing a PROM product with a mask ROM product when switching from preproduction to volume production, perform sufficient evaluation using a CS version (not ES version) of the mask ROM product.
11
PD784915A, 784916A
2. PIN FUNCTIONS
2.1 Port Pins
Pin Name P00-P07 I/O I/O Alternate Function Real-time output port 8-bit I/O port (port 0). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors (P00-P07). P40-P47 I/O 8-bit I/O port (port 4). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors (P40-P47). P50-P57 I/O 8-bit I/O port (port 5). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors (P50-P57). P60 P61 P62 P63 P64 P65 P66 P67 P70-P77 P80 P82 Input I/O HWIN PWM4 PWM5 ANI0-ANI7 Real-time output port 8-bit input port (port 7) Pseudo VSYNC output HASW output 7-bit I/O port (port 8). * Can be set in input or output mode in 1-bit units. P83 ROTC output * Can be connected with software pullup resistors (P80, P82-P87). P84 P85 P86 P87 P90 P91-P95 P96 I/O PWM2 PWM3 PTO10 PTO11 ENV KEY0-KEY4 7-bit I/O port (port 9). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors (P90-P96). I/O STRB/CLO SCK1/BUZ SO1 SI1 8-bit I/O port (port 6). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors (P60-P67). Function
12
PD784915A, 784916A
2.2 Pins Other Than Port Pins (1/2)
Pin Name REEL0IN REEL1IN DFGIN DPGIN CFGIN CSYNCIN CFGCPIN CFGAMPO PTO00 PTO01 PTO02 PTO10 PTO11 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 HASW ROTC ENV SI1 SO1 SCK1 SI2 SO2 SCK2 BUSY STRB ANI0-ANI7 ANI8-ANI11 CTLIN CTLOUT1 CTLOUT2 RECCTL+, RECCTL- CTLDLY VREFC NMI INTP0-INTP2 INTP3 KEY0-KEY4 CLO BUZ Output I/O I/O Input Input Input Input Output Output Output Output Input Input Output I/O Input Output I/O Input Output Analog input SI2 P60/CLO P70-P77 REEL0IN P91-P95 P60/STRB P61/SCK1 Key input signal input Clock output Buzzer output CTL amplifier input capacitor connection CTL amplifier output Logic signal input/CTL amplifier output RECCTL signal output/PBCTL signal input External time constant connection (for RECCTL rewriting) VREF amplifier AC connection Non-maskable interrupt request input External interrupt request input P84 P85 P66 P67 P82 P83 P90 P63 P62 P61/BUZ BUSY Head amplifier switch signal output Chroma rotation signal output Envelope signal input Serial data input (serial interface channel 1) Serial data output (serial interface channel 1) Serial clock I/O (serial interface channel 1) Serial data input (serial interface channel 2) Serial data output (serial interface channel 2) Serial clock I/O (serial interface channel 2) Serial busy signal input (serial interface channel 2) Serial strobe signal output (serial interface channel 2) Analog signal input of A/D converter Output P86 P87 PWM output of super timer unit Output Output I/O Input Alternate Function INTP3 Drum FG, PFG input (ternary) Drum PG input Capstan FG input Composite SYNC input CFG comparator input CFG amplifier output Programmable timer output of super timer unit Reel FG input Function
13
PD784915A, 784916A
2.2 Pins Other Than Port Pins (2/2)
Pin Name HWIN RESET X1 X2 XT1 XT2 AVDD1, AVDD2 AVSS1, AVSS2 AVREF VDD VSS IC I/O Input Input Input Input Crystal connection for subsystem clock oscillation. Crystal connection for watch clock oscillation Positive power supply to analog circuits GND of analog circuits Reference voltage input to A/D converter Positive power supply to digital circuits GND of digital circuits Internally connected. Directly connect this pin to VSS. Alternate Function P65 Function External input of hardware watch counter Reset input Crystal connection for main system clock oscillation
14
PD784915A, 784916A
2.3 I/O Circuits and Connection of Unused Pins Table 2-1 shows the I/O circuit type of each pin and the recommended connection of unused pins. For the configuration of each type of I/O circuit, refer to Figure 2-1. Table 2-1. I/O Circuit Type of each Pin and Recommended Connection of Unused Pins (1/2) Pin P00-P07 P40-P47 P50-P57 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 P64 P65/HWIN P66/PWM4 P67/PWM5 P70/ANI0-P77/ANI7 P80 P82/HASW P83/ROTC P84/PWM2 P85/PWM3 P86/PTO10 P87/PTO11 P90/ENV P91/KEY0-P95/KEY4 P96 SI2/BUSY SO2 SCK2 ANI8-ANI11 RECCTL+, RECCTL- 8-A 5-A 2-A 4 8-A 7 Input Output I/O Input I/O Connect to VDD Hi-Z: Connect to VSS via pull-down resistor Others: Open Input: Connect to VDD Output: Open Connect to VSS When ENCTL = 0 and ENREC = 0: Connect to VSS 9 5-A Input I/O Connect to VSS Input: Connect to VDD Output: Open 8-A 5-A 8-A 5-A 8-A 5-A I/O Circuit Type 5-A I/O I/O Recommended Connection of Unused Pins Input: Connect to VDD Output: Open
Remark ENCTL : bit 1 of amplifier control register (AMPC) ENREC: bit 7 of amplifier mode register 0 (AMPM0)
15
PD784915A, 784916A
Table 2-1. I/O Circuit Type of each Pin and Recommended Connection of Unused Pins (2/2) Pin DFGIN DPGIN CFGIN, CFGCPIN CSYNCIN REEL0IN/INTP3, REEL1IN CTLOUT1 CTLOUT2 CFGAMPO CTLIN VREFC CTLDLY PWM0, PWM1 PTO00-PTO02 NMI INTP0 INTP1, INTP2 AVDD1, AVDD2 AVREF, AVSS1, AVSS2 RESET XT1 XT2 IC Remark ENDRUM ENCAP ENCSYN ENREEL ENCTL ENCOMP 2 Connect to VSS Open Directly connect to VSS : bit 2 of amplifier control register (AMPC) : bit 3 of amplifier control register (AMPC) : bit 5 of amplifier control register (AMPC) : bit 6 of amplifier control register (AMPC) : bit 1 of amplifier control register (AMPC) : bit 4 of amplifier control register (AMPC) 2-A Input 2 Input Connect to VDD Connect to VDD or VSS Connect to VDD Connect to VDD Connect to VSS 3 Output Output I/O Output I/O Circuit Type I/O Input Recommended Connection of Unused Pins When ENDRUM = 0: Connect to VSS When ENDRUM = 0 or ENDRUM = 1 and SELPGSEPA = 0: Connect to VSS When ENCAP = 0: Connect to VSS When ENCSYN = 0: Connect to VSS When ENREEL = 0: Connect to VSS Open When ENCTL = 0 and ENCOMP = 0: Connect to VSS When ENCTL = 1: Open Open When ENCTL = 0: Open When ENCTL = 0 and ENCAP = 0 and ENCOMP = 0: Open Open Open
SELPGSEPA : bit 2 of amplifier mode register 0 (AMPM0)
16
PD784915A, 784916A
Figure 2-1. I/O Circuits of Pins (1/2)
Type 2 Type 5-A
IN pullup enable VDD data VDD pullup enable output disable input enable N-ch P-ch
VDD
Schmitt trigger input with hysteresis characteristics
P-ch
Type 2-A
IN/ OUT
P-ch IN
Schmitt trigger input with hysteresis characteristics
Type 3 Type 7
VDD P-ch data N-ch VREF (threshold voltage) OUT IN P-ch N-ch
+ -
Comparator
Type 4
Type 8-A
VDD pullup enable VDD OUT data P-ch IN/ OUT output disable N-ch
VDD data P-ch
P-ch
output disable
N-ch
Push-pull output that can make output high impedance (both P-ch and N-ch are off)
17
PD784915A, 784916A
Figure 2-1. I/O Circuits of Pins (2/2)
Type 9
IN
P-ch N-ch
+ -
Comparator
VREF (threshold voltage) input enable
18
PD784915A, 784916A
3. INTERNAL BLOCK FUNCTIONS
3.1 CPU Registers 3.1.1 General-purpose registers The PD784916A has eight banks of general-purpose registers. One bank consists of sixteen 8-bit generalpurpose registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. Four of the 16-bit generalpurpose registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register. These eight banks of general-purpose registers can be selected by software or context switching function. The general-purpose registers, except for the address expansion registers V, U, T, and W, are mapped to the internal RAM. Figure 3-1. Configuration of General-Purpose Registers
A (R1) B (R3) R5 RP2 R7 RP3 V VVP (RG4) U UUP (RG5) T R11 R9 VP (RP4)
X (R0) AX (RP0) C (R2) R4 R6 R8
BC (RP1)
R10 UP (RP5)
D (R13) E (R12) DE (RP6) TDE (RG6) H (R15) L (R14) HL (RP7) WHL (RG7) ( ): absolute name
W
8 banks
Caution
Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the RSS bit is planned to be deleted from the future models in the 78K/IV Series.
19
PD784915A, 784916A
3.1.2 Other CPU registers (1) Program counter The program counter of the PD784916A is 20 bits wide. The value of the program counter is automatically updated as the program is executed.
19 PC 0
(2) Program status word This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the program is executed.
15 14 13 12 UF RBS2 RBS1 RBS0 7 S 6 Z 5 RSS
Note
11
10
9
8
PSWH PSW PSWL
4 AC
3 IE
2 P/V
1 0
0 CY
Note
The RSS flag is provided to maintain compatibility with the microcomputers in the 78K/III Series. Always clear this flag to 0 except when the software of the 78K/III Series is used.
(3) Stack pointer This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits.
23 00 20 0 0
SP
0
3.2 Memory Space The PD784916A can access a 64K-byte memory space. The addresses of the internal ROM and internal data areas are as follows: Table 3-1. Memory Space
Part Number Internal ROM Area 0000H-BFFFH 0000H-F7FFH Internal Data Area FA00H-FFFFH
PD784915A PD784916A
Caution
Some products in the 78K/IV Series can access up to 1 Mbyte of memory space in an address expansion mode which is set by the LOCATION instruction. However, the memory space of the
PD784916A is 64K bytes (0000H through FFFFH). Therefore, be sure to execute the LOCATION
0 instruction immediately after reset to set the memory space to 64 Kbytes (the LOCATION instruction cannot be used more than once).
20
PD784915A, 784916A
Figure 3-2. Memory Map of PD784915A
FEFFH General-purpose registers (128 bytes) FE80H FE7FH FE3BH Macro service control FE06H word area (54 bytes) FD00H FCFFH Data area (512 bytes) Program/data area (768 bytes) FA00H
FFFFH FF00H FEFFH
Special function register (SFR) (256 bytes) Internal RAM (1280 bytes)
Data memory Memory space (64 Kbytes)
FA00H F9FFH
BFFFH Cannot be used 1000H 0FFFH C000H BFFFH Program memory/ data memory 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area (2 Kbytes) Program/data area (48 Kbytes)
Internal ROM (48 Kbytes)
CALLT table area (64 bytes) Vector table area (64 bytes)
0000H
21
PD784915A, 784916A
Figure 3-3. Memory Map of PD784916A
FEFFH General-purpose registers (128 bytes) FE80H FE7FH FE3BH Macro service control FE06H word area (54 bytes) FD00H FCFFH Data area (512 bytes) Program/data area (768 bytes) FA00H Cannot be used F800H F7FFH F7FFH Program/data area (62 Kbytes) Program memory/ data memory 1000H 0FFFH Internal ROM (62 Kbytes) 0800H 07FFH 0080H 007FH 0040H 003FH 0000H 0000H CALLF entry area (2 Kbytes)
FFFFH FF00H FEFFH
Special function register (SFR) (256 bytes) Internal RAM (1280 bytes)
Data memory Memory space (64 Kbytes)
FA00H F9FFH
CALLT table area (64 bytes) Vector table area (64 bytes)
22
PD784915A, 784916A
3.3 Special Function Registers (SFRs) Special function registers are assigned special functions and mapped to a 256-byte space from addresses FF00H through FFFFH. These registers include mode registers and control registers that control the internal peripheral hardware units. Caution Do not access an address to which no SFR is assigned. If such an address is accessed by mistake, the PD784916A may be deadlocked. This deadlock can be cleared only by reset input. Table 3-2 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: * Abbreviation ............................ Abbreviation of an SFR. This abbreviation is reserved for NEC's assembler (RA78K4). With a C compiler (CC78K4), the abbreviation can be used as an sfr variable by the #pragma sfr instruction. * R/W ......................................... Indicates whether the SFR in question can be read or written. R/W : Read/write R W : Read only : Write only
* Bit length ................................. Indicates the bit length (word length) of the SFR. * Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. Specify an even address to manipulate this SFR. An SFR that can be manipulated in 1-bit units can be described for a bit manipulation instruction. * After reset ............................... Indicates the status of each register after the RESET signal has been input.
23
PD784915A, 784916A
Table 3-2. Special Function Registers (1/4)
Bit Address Special Function Register (SFR) Name Symbol R/W Length Bit Units for Manipulation 1 bit FF00H FF04H FF05H FF06H FF07H FF08H FF09H FF0EH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF1AH FF1CH FF1EH FF20H FF24H FF25H FF26H FF28H FF29H FF2EH FF30H FF31H FF32H FF34H FF35H FF36H FF38H FF39H FF3AH FF3BH Port 0 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 0 buffer register L Port 0 buffer register H Timer 0 compare register 0 Event counter compare register 0 Timer 0 compare register 1 Event counter compare register 1 Timer 0 compare register 2 Event counter compare register 2 Timer 1 compare register 0 Event counter compare register 3 Timer 1 compare register 1 Timer 1 compare register 2 Timer 1 compare register 3 Timer 2 compare register 0 Port 0 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 8 mode register Port 9 mode register Real-time output port 0 control register Timer register 0 Event counter Timer register 1 Free running counter (bits 0 to 15) Free running counter (bits 16 to 21) Timer register 2 Timer control register 0 Timer control register 1 Timer control register 2 Timer control register 3 P0 P4 P5 P6 P7 P8 P9 P0L P0H CR00 ECC0 CR01 ECC1 CR02 ECC2 CR10 ECC3 CR11 CR12 CR13 CR20 PM0 PM4 PM5 PM6 PM8 PM9 RTPC TM0 EC TM1 FRCL FRCH TM2 TMC0 TMC1 TMC2 TMC3 R/W R/W R R/W R W W R/W W R/W W R/W W R/W R R/W R R/W R/W 8 8 8 8 8 8 8 8 8 16 8 16 8 16 8 16 8 16 16 16 16 8 8 8 8 8 8 8 16 8 16 16 8 16 8 8 8 8 00x00000 0000H 00H Cleared to 0 00H FDH 7FH 00H Cleared to 0 FFH 8 bits 16 bits Cleared to 0 After Releasing Reset Undefined
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the contents before initialization are undefined).
24
PD784915A, 784916A
Table 3-2. Special Function Registers (2/4)
Bit Address Special Function Register (SFR) Name Symbol R/W Length 1 bit FF3CH FF3DH FF3EH FF48H FF4DH FF4EH FF4FH FF50H FF51H FF52H FF53H FF54H FF56H FF58H FF59H FF5AH FF5BH FF5CH FF5EH FF60H FF63H FF65H FF66H FF68H Timer register 3 Timer control register 4 Timer register 4 Port 8 mode control register Trigger source select register Pull-up resistor option register L Pull-up resistor option register H Input control register Up/down counter count register Event divider counter Capture mode register Timer register 5 Timer 3 capture register 0 Timer 0 output mode register Timer 0 output control register Timer 1 output mode register Timer 1 output control register Timer 3 compare register 0 Timer 3 compare register 1 Port 8 buffer register L Up/down counter compare register Trigger source select register 1 Port 6 mode control register A/D converter mode register TM3 TMC4 TM4 PMC8 TRGS0 PUOL PUOH ICR UDC EDV CPTM TM5 CPT30 TOM0 TOC0 TOM1Note 1 TOC1 CR30 CR31 P8L UDCC TRGS1 PMC6 ADM ADMLNote 2 FF6AH FF6CH FF6EH FF6FH FF70H FF71H FF72H FF73H FF74H FF75H A/D conversion result register Hardware watch counter 0 Hardware watch counter 1 Watch mode register PWM control register 0 PWM control register 1 PWM0 modulo register PWM2 modulo register PWM1 modulo register PWM3 modulo register ADCR HW0 HW1 WM PWMC0 PWMC1 PWM0 PWM2 PWM1 PWM3 R R/W R R/W R/W W R/W R/W W R/W W R R/W R R R/W R R/W 16 8 16 8 8 8 8 8 8 8 8 16 16 8 8 8 8 16 16 8 8 8 8 16 8 8 16 16 8 8 8 16 8 16 8 Undefined Not affected by reset 00xx0x00 05H 15H 0000H 00H 0000H 00H 0000H 000x0x0x Undefined 00H xx000000 00H 80H 00H Cleared to 0 10H Undefined Cleared to 0 00H Cleared to 0 Bit Units for Manipulation 8 bits 16 bits After Releasing Reset Cleared to 0 xx000000 Cleared to 0 00H
Notes 1. When the timer 1 output mode register (TOM1) is read, the write sequence of the REC driver is read (bits 0 and 1). 2. ADML is the lower 8 bits of the A/D converter mode register (ADM) and can be manipulated in 1- or 8bit units. Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the contents before initialization are undefined).
25
PD784915A, 784916A
Table 3-2. Special Function Registers (3/4)
Bit Address Special Function Register (SFR) Name Symbol R/W Length Bit Units for Manipulation 1 bit FF76H FF77H FF78H FF79H FF7AH FF7BH FF7CH FF7DH FF7EH FF84H FF85H FF88H FF89H FF8AH FF91H FF94H FF95H FF96H FF97H FFA0H FFA1H FFA2H FFA6H FFA8H PWM5 modulo register PWM4 modulo register Event divider control register Clock output mode register Timer 4 capture/compare register 0 Clock control register Timer 4 capture register 1 Capture/compare control register Timer 5 compare register Serial mode register 1 Serial shift register 1 Serial mode register 2 Serial shift register 2 Serial control register 2 Head amplifier switch output control register Amplifier control register Amplifier mode register 0 Amplifier mode register 1 Gain control register External interrupt mode register External capture mode register 1 External capture mode register 2 Key interrupt control register In-service priority register PWM5 PWM4 EDVC CLOM CR40 CC CR41 CRC CR50 CSIM1 SIO1 CSIM2 SIO2 CSIC2 HAPC AMPC AMPM0 AMPM1 CTLM INTM0 INTM1 INTM2 KEYC ISPR IMC MK0L MK0H MK1L MK1H FRC capture register 0L FRC capture register 0H FRC capture register 1L FRC capture register 1H FRC capture register 2L FRC capture register 2H FRC capture register 3L FRC capture register 3H FRC capture register 4L CPT0L CPT0H CPT1L CPT1H CPT2L CPT2H CPT3L CPT3H CPT4L R MK0 R R/W R W R/W W R/W R/W 16 8 8 8 16 8 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 8 16 8 16 8 16 Cleared to 0 70H 00H 80H FFH 000000x0 00H 8 bits 16 bits After Releasing Reset 0000H 00H 00H 00H Cleared to 0 00H Cleared to 0 00H Cleared to 0 00H Undefined 00H Undefined 00H
FFAAH Interrupt mode control register FFACH Interrupt mask flag register FFADH FFAEH FFAFH FFB0H FFB1H FFB2H FFB3H FFB4H FFB5H FFB6H FFB7H FFB8H
MK1
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the contents before initialization are undefined).
26
PD784915A, 784916A
Table 3-2. Special Function Registers (4/4)
Bit Address Special Function Register (SFR) Name Symbol R/W Length 1 bit FFB9H FRC capture register 4H CPT4H CPT5L CPT5H STBC MM PCS OSTS PIC0 CPTIC3 CPTIC2 CRIC12 CRIC00 CLRIC1 CRIC10 CRIC01 CRIC02 CRIC11 CPTIC1 CRIC20 TBIC ADIC PIC2 CRIC40 UDCIC CRIC30 CRIC50 CRIC13 CSIIC1 WIC PIC1 PIC3 CSIIC2 8 8 8 8 8 8 8 8 8 R/W W R W R/W R 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 43H 0000x000 20H 00H Bit Units for Manipulation 8 bits 16 bits After Releasing Reset Cleared to 0
FFBAH FRC capture register 5L FFBBH FRC capture register 5H FFC0H FFC4H Standby control register Execution speed select register
FFCEH CPU clock status register FFCFH Oscillation stabilization time specification register FFE0H FFE1H FFE2H FFE3H FFE4H FFE5H FFE6H FFE7H FFE8H FFE9H Interrupt control register (INTP0) Interrupt control register (INTCPT3) Interrupt control register (INTCPT2) Interrupt control register (INTCR00) Interrupt control register (INTCR00) Interrupt control register (INTCLR1) Interrupt control register (INTCR10) Interrupt control register (INTCR01) Interrupt control register (INTCR02) Interrupt control register (INTCR11)
FFEAH Interrupt control register (INTCPT1) FFEBH Interrupt control register (INTCR20) FFEDH Interrupt control register (INTTB) FFEEH Interrupt control register (INTAD) FFEFH Interrupt control register (INTP2)Note Interrupt control register (INTCR40)Note FFF0H FFF1H FFF2H FFF3H FFF4H FFF5H FFF7H FFF8H FFFAH Interrupt control register (INTUDC) Interrupt control register (INTCR30) Interrupt control register (INTCR50) Interrupt control register (INTCR13) Interrupt control register (INTCSI1) Interrupt control register (INTW) Interrupt control register (INTP1) Interrupt control register (INTP3) Interrupt control register (INTCSI2)
Note
PIC2 and CRIC40 are at the same address (register).
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been deasserted (the contents before initialization are undefined).
27
PD784915A, 784916A
3.4 PORTS The PD784916A is provided with the ports shown in Figure 3-4. Table 3-3 shows the function of each port. Figure 3-4. Port Configuration
P00 Port 0 P07 P40 Port 4 P47 P50 Port 5 P57
P60 Port 6 P67 P70-P77 P80 P82 Port 8 P87 P90 Port 9 P96 8 Port 7
Table 3-3. Port Function Name Port 0 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Pin Name P00-P07 P40-P47 P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96 Input port Can be set in input or output mode in 1-bit units. Pull-up resistor is not provided. Pull-up resistors are connected to all pins in input mode. 1-bit units. Function Can be set in input or output mode in Specification of Pull-up Resistor Pull-up resistors are connected to all pins in input mode.
28
PD784915A, 784916A
3.5 Real-time Output Port A real-time output port consists of a port output latch and a buffer register (refer to Figure 3-5). The function to transfer the data prepared in advance in the buffer register to the output latch when a trigger such as a timer interrupt occurs, and output the data to an external device is called a real-time output function. A port used in this way is called a real-time output port (RTP). Table 3-4 shows the real-time output ports of the PD784916A. Table 3-5 shows the trigger sources of RTPs. Figure 3-5. Configuration of RTP
Buffer register Output trigger Port output latch
Port
Table 3-4. Bit Configuration of RTP Alternate RTP RTP0 RTP8 Function Port 0 Port 8 Number of Bits of Real-Time Output Data 4 bits x 2 channels or 8 bits x 1 channel 1 bit x 1 channel and 2 bits x 1 channel 1-bit units Pseudo VSYNC output: 1 channel (RTP80) Head amplifier switch: 1 channel (RTP82) Chrominance rotation signal output: 1 channel (RTP83) Table 3-5. Trigger Sources of RTP Trigger Source RTP RTP0 Higher 4 bits Lower 4 bits All 8 bits RTP8 Bit 0 Bits 2 and 3 Notes 1. Select one of the four trigger sources. 2. When the real-time output port mode is set by the port mode control register 8 (PMC8), the HASW and ROT-C signals that are set by the head amplifier switch output control register (HAPC) are directly output. The HASW and ROT-C signals are synchronized with HSW output (TM0-CR00 coincidence signal). However, the set signal is output immediately when the HAPC register is rewritten. Note 1 Note 2 INTCR00 INTCR01 INTCR02 INTCR13 INTCR50 INTCR0 Remark Number of Bits That Can Be Specified as RTP 4-bit units Remark
29
PD784915A, 784916A
Figures 3-6 and 3-7 show the block diagrams of RTP0 and RTP8. Figure 3-8 shows the types of RTP output trigger sources. Figure 3-6. Block Diagram of RTP0
Internal bus 8 Real-time output port 0 control register 4 4
Buffer register P0H P0L 4 4
8
INTP0 INTCR01 INTCR02
Output trigger Control circuit
Output latch (P0)
P07
P00
Remark INTCR01: TM0-CR01 coincidence signal INTCR02: TM0-CR02 coincidence signal Figure 3-7. Block Diagram of RPT8
Internal bus 8 Head amplifier output control register (HAPC) SEL SEL SEL PB PB PB 00 ROTC HASW ENV MOD2 MOD1 MOD0 TRGP80 HASW, ROT-C TM0-CR00 control circuit coincidence signal PMC80 0 PMC82 PMC83 PMC8 Output latch (P8) 8 Port 8 buffer register L (P8L) SEL 0 0 0 P8L4 P8L2 0 P8L0 MD80 Pseudo VSYNC output control circuit 8
HSYNC superimposition circuit P83 P82 P80
30
PD784915A, 784916A
Figure 3-8. Types of RTP Output Trigger Sources
Real-time output port 0 control register (RTPC) INTP0
TM0
Selector
Trigger of P0H Trigger of P0L
CR00 CR01 CR02 Selector TM1 Trigger of P80 Interrupt and timer output
Trigger of P82 and P83
CR10 CR11 Capture CR12
Interrupt and timer output
Trigger source select register 0 (TRGS0)
Interrupt CR13
TM5
CR50
Interrupt
31
PD784915A, 784916A
RTP80 can output low-level, high-level, and high-impedance values real-time. Because RTP80 can superimpose a horizontal sync signal, it can be used to create a pseudo vertical sync signal. When RTP80 is set in the pseudo VSYNC output mode, it repeatedly outputs a specific pattern when an output trigger occurs. Figure 3-9 shows the operation timing of RTP80. Figure 3-9. Example of Operation Timing of RTP80 (a) When HSYNC signal is superimposed
High level P80 High impedance Low level Trigger signal
(b) Pseudo VSYNC output mode
High level P80 High impedance Low level Trigger signal
32
PD784915A, 784916A
3.6 Super Timer Unit The PD784916A is provided with a super timer unit that consists of the timers shown in Table 3-6. Table 3-6. Configuration of Super Timer Unit
Maximum Count Time 65.5 ms
Unit Name Timer 0
Timer/Counter TM0 (16-bit timer)
Resolution 1 s
Register CR00 CR01 CR02
Remark Controls delay of video head switching signal Controls delay of audio head switching signal Controls pseudo VSYNC output timing Creates internal head switching signal
EC (8-bit counter) Free running FRC counter (22-bit counter)
-
-
ECC0, ECC1, ECC2, ECC3
125 ns
524 ms
CPT0 CPT1
Detects reference phase (to control drum phase) Detects phase of drum motor (to control drum phase)
CPT2
Detects speed of drum motor (to control drum speed)
CPT3
Detects speed of capstan motor (to control speed of capstan motor)
CPT4, CPT5 Timer 1 TM1 (16-bit timer) 1 s 65.5 ms CR10
Detects remaining tape for reel FG Playback: Creates internal reference signal Recording: Buffer oscillator in case VSYNC is missing
CR11 CR12
Controls RECCTL output timing Detects phase of capstan motor (to control capstan phase)
CR13 1 s or 1.1 s 65.5 ms or 71.5 ms CPT30 EDV (8-bit counter) Timer 2 TM2 (16-bit timer) Timer 4 TM4 (16-bit timer) CR41 2 s 2 s 131 ms CR40 1 s 65.5 ms CR20 EDVC
Controls VSYNC mask as noise prevention measures
TM3 (16-bit timer)
CR30, CR31
Controls duty detection timing of PBCTL signal Measures cycle of PBCTL signal Divides CFG signal frequency
Can be used as interval timer (to control system) Detects duty of remote controller signal (to decode remote controller signal) Measures cycle of remote controller signal (to decode remote controller signal)
Timer 5
TM5 (16-bit timer)
131 ms
CR50
Can be used as interval timer (to control system)
Up/down counter PWM output unit
UDC (5-bit counter) -
-
-
UDCC
Creates linear tape counter
-
-
PWM0, PWM1, 16-bit resolution (carrier frequency: 62.5 kHz) PWM5 PWM2, PWM3, 8-bit resolution (carrier frequency: 62.5 kHz) PWM4
33
PD784915A, 784916A
(1) Timer 0 unit Timer 0 unit creates head switching signal and pseudo VSYNC output timing from the PG and FG signals of the drum motor. This unit consists of an event counter (EC: 8 bits), four compare registers (ECC0 through ECC3), a timer (TM0: 16 bits), and three compare registers (CR00 through CR02). A signal indicating coincidence between the value of timer 0 and the value of a compare register can be used as the output trigger of the real-time output port. (2) Free running counter unit The free running counter unit detects the speed and phase of the drum motor, and the speed and reel speed of the capstan motor. This unit consists of a free running counter (FRC), six capture registers (CPT0 through CPT5), a VSYNC separation circuit, and a HSYNC separation circuit. (3) Timer 1 unit Timer 1 unit is a reference timer unit synchronized with the frame cycle and creates the RECCTL signal, detects the phase of the capstan motor, and detects the duty factor of the PBCTL signal. This unit consists of the following three groups: * Timer 1 (TM1), compare registers (CR10, CR11, and CR13), and capture register (CR12) * Timer 3 (TM3), compare registers (CR30 and CR31), and capture register (CPT30) * Event divider counter (EDV) and compare register (EDVC) The TM1-CR13 coincidence signal can be used for automatic unmasking of VSYNC or as the output trigger of the real-time output port.
34
Figure 3-10. Block Diagram of Super Timer Unit (TM0, FRC, TM1)
Selector Selector Selector Clear TM0 CR00 CR01 CR02
DPGIN Divider Selector Selector Writes 00H to EC DFGIN Selector Clear EC ECC3 ECC2 ECC1 ECC0 Selector F/F F/F Mask
Output control circuit Output control circuit Output control circuit (Superimposition) RTP RTP, A/D INTCR00
PTO00 PTO01 INTCR01 PTO02 INTCR02
Analog circuit
RTP, A/D (Superimposition)
HSYNC separation circuit Selector
To P80 INTCLR1
CSYNCIN
VSYNC separation circuit
Selector
Selector
FRC Capture Capture Capture Capture Capture Capture CPT0 CPT1 CPT2 CPT3 CPT4 CPT5 Selector
REEL0IN
Mask
INTCPT1 INTCPT2 INTCPT3
REEL1IN
Selector
PD784915A, 784916A
INTP3 Output control circuit PTO10 INTCR10 Output control circuit INTCR11 INTCR12 INTCR13 INTCR30 To PBCTL signal input block PTO11
Selector
CFGIN
Clear EDV EDVC Selector Selector Clear TM1 CR10 CR11 CR12 CR13
PBCTL PTO10 PTO11
Selector
Clear TM3 CR30 CR31 Capture CPT30
Capture
CTL F/F
FFLVL
35
PD784915A, 784916A
(4) Timer 2 unit Timer 2 unit is a general-purpose 16-bit timer unit. This unit consists of a timer 2 (TM2) and a compare register (CR20). The timer is cleared when the TM2-CR20 coincidence signal occurs, and at the same time, an interrupt is generated. Figure 3-11. Block Diagram of Timer 2 Unit
Clear TM2
CR20
INTCR20
(5) Timer 4 unit Timer 4 unit is a general-purpose 16-bit timer unit. This unit consists of a timer 4 (TM4), a capture/compare register (CR40), and a capture register (CR41). The value of the timer is captured to CR40/CR41 when the INTP2 signal is input. This timer can be used to decode a remote controller signal. Figure 3-12. Block Diagram of Timer 4 Unit
Mask Clear TM4
Selector
INTP2
CR40 CR41
INTCR40
(6) Timer 5 unit Timer 5 unit is a general-purpose 16-bit timer unit. This unit consists of a timer 5 (TM5) and a compare register (CR50). The timer is cleared by the TM5-CR50 coincidence signal, and at the same time, an interrupt is generated. Figure 3-13. Block Diagram of Timer 5 Unit
Clear TM5
CR50
INTCR50 RTP, A/D
36
PD784915A, 784916A
(7) Up/down counter unit The up/down counter unit is a counter that realizes a linear time counter. This unit consists of an up/down counter (UDC) and a compare register (UDCC). The up/down counter counts up the rising edges of PBCTL and counts down the falling edges of PBCTL. When the value of the up/down counter coincides with the value of the compare register, or when the counter underflows, an interrupt is generated. Figure 3-14. Block Diagram of Up/Down Counter Unit
Selector
SELUD PTO10 PTO11 P77 EDVC output
Selector
UP/DOWN UDC
Selector
PBCTL
Selector
UDCC
INTUDC
(8) PWM output unit The PWM output unit has three 16-bit accuracy output lines (PWM0, PWM1, and PWM5) and 8-bit accuracy output lines (PWM2 through PWM4). The carrier frequency of all the output lines is 62.5 kHz (fCLK = 8 MHz). PWM0 and PWM1 can be used to control the drum motor and capstan motor. Figure 3-15. Block Diagram of 16-Bit PWM Output Unit
(n = 0, 1, 5) Internal bus 16 PWMn 15 8 Reload 87 8 Reload Reload control 0 8
PWMC0 To selector
16 MHz
8-bit down counter
PWM pulse generation circuit 8-bit counter
Output control circuit
PWMn
1/256
RESET
37
PD784915A, 784916A
Figure 3-16. Block Diagram of 8-Bit PWM Output Unit
Internal bus
PWM2
PWM3
PWM4
PWMC1
8-bit comparator
8-bit comparator
8-bit comparator Output control circuit
PWM4
16 MHz
PWM counter
Output control circuit
PWM3
Output control circuit
PWM2
3.7 Serial Interface The PD784916A is provided with the serial interfaces shown in Table 3-7. Data can be automatically transmitted or received through these serial interfaces, when the macro service is used. Table 3-7. Types of Serial Interfaces Name Serial interface channel 1 * Clocked serial interface (3-wire) * Bit length: 8 bits * Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) * MSB first/LSB first selectable Serial interface channel 2 * Clocked serial interface (3-wire) * Bit length: 8 bits * Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) * MSB first/LSB first selectable * BUSY/STRB control function Function
38
PD784915A, 784916A
Figure 3-17. Block Diagram of Serial Interface Channel n (n = 1 or 2)
Internal bus
SIn /BUSY
Selector
SIOn register
CSIM register
SOn
Serial clock counter SCKn
INTCSIn
Busy detection circuit
fCLK/8 fCLK/16 fCLK/32 fCLK/64 fCLK/128 fCLK/256
STRB
Strobe generation circuit
CSIC2 register
Internal bus
Remark The circuits enclosed in the broken line are provided for serial interface channel 2 only.
Selector
39
PD784915A, 784916A
3.8 A/D Converter The PD784916A has an analog-to-digital (A/D) converter with 12 multiplexed analog inputs (ANI0 through ANI11). This A/D converter is of successive approximation type, and the conversion result is held by an 8-bit A/D conversion result register (ADCR) (conversion time: 10 s at fCLK = 8 MHz). A/D conversion can be started in the following two modes: * Hardware start : Conversion is started by a hardware triggerNote. * Software start : Conversion is started by setting the A/D conversion mode register (ADM). After conversion has been started, the A/D converter operates in the following modes: * Scan mode : Sequentially selects more than one analog input to obtain data to be converted from all the pins. * Select mode: Use only one pin for analog input to obtain successive data. When the conversion result is transferred to ADCR, interrupt request INTAD is generated. By processing this interrupt with the macro service, the conversion result can be successively transferred to memory. A mode in which starting A/D conversion of the next pin is kept pending until the value of ADCR is read is also available. When this mode is used, reading the conversion result by mistake when timing is shifted because an interrupt is disabled can be prevented. Note A hardware trigger can be one of the following coincidence signals, one of which is selected by the trigger source select register 1 (TRGS1): * TM0-CR01 coincidence signal * TM0-CR02 coincidence signal * TM1-CR13 coincidence signal * TM5-CR50 coincidence signal
40
PD784915A, 784916A
Figure 3-18. Block Diagram of A/D Converter
ANI0
Input selector
ANI1 ANI2 ANI3 . . . ANI11
Sample & hold circuit
Series resistor string AVREF Voltage comparator R/2
Tap selector
. . .
R
Successive approximation register (SAR)
Selector
TM0-CR01 coincidence TM0-CR02 coincidence TM1-CR13 coincidence TM5-CR50 coincidence
Conversion trigger Control circuit Trigger enable 8 Delay detection circuit INTAD A/D conversion end interrupt
R/2 AVSS2
Trigger source select register 1 (TRGS1) A/D converter mode register (ADM) 16
A/D conversion result register (ADCR) 8 Internal bus
3.9 VCR Analog Circuits The PD784916A is provided with the following VCR analog circuits: * CTL amplifier * RECCTL driver (rewritable) * DPG comparator * DFG amplifier * DPFG separation circuit (ternary separation circuit) * CFG amplifier * Reel FG comparator (2 channels) * CSYNC comparator
41
PD784915A, 784916A
(1) CTL amplifier/RECCTL driver The CTL amplifier is used to amplify the playback control (PBCTL) signal that is reproduced from the CTL signal recorded on a VCR tape. The gain of the CTL amplifier is set by the gain control register (CTLM). Thirty-two types of gains can be set in increments of about 1.78 dB. The PD784195 is also provided with a gain control signal generation circuit that monitors the status of the amplifier output to perform optimum gain control by program. The gain control signal generation circuit generates a CTL detection flag that identifies the amplitude status of the CTL amplifier output. By using this CTL detection flag, the gain of the CTL amplifier can be optimized. The RECCTL driver writes a control signal onto a VCR tape. This driver operates in two modes: REC mode that is used for recording, and rewrite mode used to rewrite the VISS signal. The output status of the RECCTL pin is changed by hardware, by using the timer output from the super timer unit as a trigger. Figure 3-19. Block Diagram of CTL Amplifier and RECCTL Driver
ANI11 CTLDLY
TOM1.4-TOM1.6 Selector TM1-CR11 coincidence signal TM1-CR13 coincidence signal TM3-CR30 coincidence signal
RECCTL+
RECCTL driver
RECCTL-
CTL head
VREF AMPC. 1 + -
AMPC. 1 CTLIN CTLOUT1 CTLM. 0-CTLM. 4 CTLOUT2 Waveform shaping circuit PBCTL signal (to timer unit) + Gain control signal generation circuit CTL detection flag L (AMPM0. 1) CTL detection flag S (AMPM0. 3) CTL detection flag clear (1 write to AMPM0. 6)
42
PD784915A, 784916A
(2) DPG comparator, DFG amplifier, and DPFG separation circuit The DPG comparator converts the drum PG (DPG) signal that indicates the phase information of the drum motor into a logic signal. The DFG amplifier amplifies the drum FG (DFG) signal that indicates the speed information of the drum motor. The DPFG separation circuit (ternary separation circuit) separates a drum PFG (DPFG) signal having speed and phase information into a DFG and DPG signals. Figure 3-20. Block Diagram of DPG Comparator, DFG Amplifier, and DPFG Separation Circuit
VREF AMPC.2 AMPM0.0 Drum PG signal DPGIN DPG comparator Selector 1 0 AMPM0.2 AMPC.2
1 Selector DPG signal (to timer unit)
0 VREF AMPC.2 AMPM0.0 Drum FG signal or drum PFG signal
+ -
DFG amplifier
DFGIN AMPM0.2 AMPM0.2 0 1 AMPC.2 AMPC.2 Selector
DPFG separation circuit (ternary separation circuit)
1 0
1 Selector DFG signal (to timer unit)
AMPM0.2
0
43
PD784915A, 784916A
(3) CFG amplifier The CFG amplifier amplifies the capstan FG (CFG) signal that indicates the speed information of the capstan motor. This amplifier consists of an operational amplifier and a comparator. The gain of the operational amplifier is set by using an external resistor. When the gain of the operational amplifier is set to 50 dB, the output duty accuracy of the CFG signal can be improved to 50.0 0.3%. Figure 3-21. Block Diagram of CFG Amplifier
VREF AMPC.3 + Capstan FG signal CFGIN CFG amplifier
CFGAMPO
AMPM0.0
VREF AMPC.3 CFG comparator
AMPC.3
CFGCPIN +
Selector
1
CFG signal (to timer unit)
0
44
PD784915A, 784916A
(4) Reel FG comparators The reel FG comparator converts a reel FG signal that indicates the speed information of the reel motor into a logic signal. Two comparators, one for take-up and the other for supply, are provided. Figure 3-22. Block Diagram of Reel FG Comparators
VREF AMPC.6 AMPM0.0 1 REEL0IN Reel FG comparator 0 VREF AMPC.6 AMPM0.0 AMPC.6
Selector
Supply reel signal
Reel FG0 signal (to timer unit)
REEL1IN Reel FG comparator 0
Selector
Take-up reel signal
1 Reel FG1 signal (to timer unit)
(5) CSYNC comparator The CSYNC comparator converts the COMPSYNC signal into a logic signal. Figure 3-23. Block Diagram of COMPSYNC Comparator
VREF AMPM1.7 AMPC.5 AMPM0.0 AMPC.5
CSYNCIN CSYNC comparator 0
Selector
COMPSYNC signal
1 CSYNC signal (to timer unit)
45
PD784915A, 784916A
(6) Reference amplifier The reference amplifier generates a reference voltage (VREF) to be supplied to the internal amplifiers and comparators of the PD784916A. Figure 3-24. Block Diagram of Reference Amplifier
AVDD1 + VREF (CFG amplifier) ENCAP (AMPC.3)
VREFC
AVSS1
+ VREF (CFG amplifier) ENCTL (AMPC.1) + VREF (CTL amplifier)
ENDRUM (AMPC.2) ENREEL (AMPC.6) ENCSYN (AMPC.5)
+ VREF DFG amplifier, DPG comparator, reel FG comparator, and CSYNC comparator)
Remark Multiple reference amplifiers are provided to assure the accuracy of the amplifiers and comparators.
46
PD784915A, 784916A
3.10 Watch Function The PD784916A has a watch function that counts the overflow signals of the watch timer by hardware. As the clock, the subsystem clock (32.768 kHz) is used. Because this watch function is independent of the CPU, it can be used even while the CPU is in the standby mode (STOP mode) or is reset. In addition, this function can be used at a low voltage of VDD = 2.7 V (MIN.). Therefore, by using only the watch function with the CPU set in the standby mode or reset, a watch operation can be performed at a low voltage and low current dissipation. In addition, the watch function can also be used while the CPU is in the normal operation mode, because a dedicated counter is provided. The watch function can be used to count up to about 17 years of data. The hardware watch counters (HW0 and HW1) are shared with external input counters. These counters execute counting at the falling edge of input to the P65 pin, and can be used to count the HSYNC signals. Figure 3-25. Block Diagram of Watch Counter
PM65 PMC65 P65 P65 Edge detection Pin level read WM.2 (enables/disables operation)
Selector
fXT (32.768 kHz)
0
13
Selector
1 0
WM.2 (enables/disables operation)
0 15 0 13
Watch timer Normal
1 Fast forward
0
HW0
HW1 WM.2
Selector
To NMI generation block
WM.1
Selector
BUZ signal WM.7
WM.6 INTW
WM.5 WM.4
47
PD784915A, 784916A
3.11 Clock Output Function The PD784916A can output a square wave (with a duty factor of 50%) to the P60/CLO pin as the operating clock for the peripheral devices or other microcomputers. To enable or disable the clock output, and to set the frequency of the clock, the clock output mode register (CLOM) is used. When setting the frequency, the division ratio can be set to fCLK/n (where n = 2, 4, 8, or 16) (fCLK = fOSC/2: fOSC is the oscillation frequency of the oscillator). Figure 3-26 shows the configuration of the clock output circuit. The clock output (CLO) pin is shared with P60. Figure 3-26. Block Diagram of Clock Output Circuit
CLOM
0
0
0
ENCLO
0
0
SELFRQ1 SELFRQ0
fCLK fCLK/2 fCLK/4 fCLK/8
Output control circuit
Selector
1/2 P60 RESET
P60/CLO
Remark fCLK: internal system clock Caution Do not use the clock output function in the STOP mode. Clear ENCLO (CLOM.4) to 0 in the STOP mode. Figure 3-27 Application Example of Clock Output Function
PD784916A PD75312
LCD 24 CLO SCK1 SI1 SO1 System clock CL1 SCK SO SI
48
PD784915A, 784916A
4. INTERNAL/EXTERNAL CONTROL FUNCTION
4.1 Interrupt Function The PD784916A has as many as 30 interrupt sources, including internal and external sources. For 26 sources, a high-speed interrupt processing mode such as context switching or macro service can be specified by software. Table 4-1 lists the interrupt sources. Table 4-1. Interrupt Sources
Interrupt Request Type Reset Nonmaskable Maskable 0 1 2 3 INTP0 INTP0 pin input edge PIC0 CPTIC3 CPTIC2 CRIC12 Yes Yes FE06H FE08H FE0AH FE0CH 0006H 0008H 000AH 000CH Priority Name RESET NMI RESET pin input NMI pin input edge Trigger Interrupt Control Register Name Macro Service Control Address Word Vector Table Address 0000H 0002H
Interrupt Request Source
Macro Service No
Context Switching No
INTCPT3 EDVC output signal (CPT3 capture) INTCPT2 DFGIN pin input edge (CPT2 capture) INTCR12 PBCTL input edge/EDVC output signal (CR12 capture)
4 5 6 7 8 9 10
INTCR00 TM0-CR00 coincidence signal INTCLR1 CSYNCIN pin input edge INTCR10 TM1-CR10 coincidence signal INTCR01 TM0-CR01 coincidence signal INTCR02 TM0-CR02 coincidence signal INTCR11 TM1-CR11 coincidence signal INTCPT1 Pin input edge/EC output signal (CPT1 capture)
CRIC00 CLRIC1 CRIC10 CRIC01 CRIC02 CRIC11 CPTIC1
FE0EH FE10H FE12H FE14H FE16H FE18H FE1AH
000EH 0010H 0012H 0014H 0016H 0018H 001AH
11 12 13 14
INTCR20 TM2-CR20 coincidence signal INTTB INTAD INTP2 Time base from FRC A/D converter conversion end INTP2 pin input edge
CRIC20 TBIC ADIC PIC2 CRIC40 UDCIC CRIC30 CRIC50 CRIC13 CSIIC1 WIC PIC1 PIC3 CSIIC2 No No
FE1CH FE20H FE22H FE24H
001CH 0020H 0022H 0024H
INTCR40 TM4-CR40 coincidence signal 15 16 17 18 19 20 21 22 23 Operand error Software INTUDC UDC-UDCC coincidence/UDC underflow INTCR30 TM3-CR30 coincidence signal INTCR50 TM5-CR50 coincidence signal INTCR13 TM1-CR13 coincidence signal INTCSI1 End of serial transfer (channel 1) INTW INTP1 INTP3 Overflow of watch timer INTP1 pin input edge INTP3 pin input edge
FE26H FE28H FE2AH FE2CH FE2EH FE30H FE34H FE36H FE3AH -
0026H 0028H 002AH 002CH 002EH 0030H 0034H 0036H 003AH 003CH
INTCSI2 End of serial transfer (channel 2) Illegal operand of MOV STBC, #byte or LOCATION instruction Execution of BRK instruction Execution of BRKCS instruction
Yes
-
003EH -
49
PD784915A, 784916A
Figure 4-1. Differences in Operation Depending on Interrupt Processing Mode
Macro service
Main routine
Macro service processing
Main routine
Context Note 1 switching
Main routine
Note 2
Interrupt processing
Note 3
Main routine
Vector Note 2 interrupt
Main routine
Note 4
SEL RBn
Interrupt processing
Restoring PC and PSW
Main routine
Vector interrupt
Main routine
Note 4
Saving general register
Initializing general register
Interrupt processing
Restoring general register
Restoring PC and PSW
Main routine
Interrupt request generated
Notes 1. When the register bank switching function is used and when initial values are set in advance to the registers 2. Selecting a register bank and saving PC and PSW by context switching 3. Restoring register bank, PC, and PSW by context switching 4. Saves PC and PSW to stack and loads vector address to PC
50
PD784915A, 784916A
4.1.1 Vector interrupt When an interrupt is acknowledged, an interrupt processing program is executed according to the data stored in the vector table area (the first address of the interrupt processing program created by the user). Four levels of priorities can be specified by software for the vector interrupts of the PD784916A. 4.1.2 Context switching When an interrupt request is generated or when the BRKCS instruction is executed, a specific register bank is selected by hardware, and execution branches to a vector address set in advance in the register bank. At the same time, the current contents of the program counter (PC) and program status word (PSW) are saved to the registers in the register bank. Because the contents of PC and PSW are not saved to the stack area, execution can be branched to an interrupt processing routine more quickly than the vector interrupt. Figure 4-2. Context Switching Operation When Interrupt Request Is Generated
<7> 0H Register bank n (n = 0-7)
PC19-16 PC15-0
Register bank (0-7) A B R5 R7 X C R4 R6 VP UP D H E L <3> Switching register bank (RSB0-RSB2 n) <4> RSS 0 IE 0
<6> Exchange <2> Save Bits 8-11 of temporary register <5> Save V U T <1> Save PSW W
Temporary register
51
PD784915A, 784916A
4.1.3 Macro service The macro service is a function to transfer data between the memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR and directly transfers the data. Because the status of the CPU is not saved or restored, data can be transferred more quickly than context switching. The processing that can be executed with the macro service is described below. Figure 4-3. Macro Service
CPU
Memory
Read Write
Macro service controller
Write Read
SFR
Internal bus
(1) Counter mode In this mode, the value of the macro service counter (MSC) is decremented when an interrupt occurs. This mode can be used to execute the division operation of an interrupt or count the number of times an interrupt has occurred. When the value of the macro service counter has been decremented to 0, a vector interrupt occurs.
MSC
-1
(2) Compound data transfer mode When an interrupt occurs, data are simultaneously transferred from an 8-bit SFR to memory, a 16-bit SFR to memory (word), memory (byte) to an 8-bit SFR, and memory (word) to a 16-bit SFR (3 points MAX. for each transfer). This mode can also be used to exchange data, instead of transferring data. This mode can be used for automatic transfer/reception by the serial interface or automatic updating of data/timing by the serial output port. When the value of the macro service counter reaches to 0, a vector interrupt occurs.
Memory
SFR<4>-1
SFR<4>-2 SFR<4>-3
SFR<3>-1
SFR<3>-2
SFR<3>-3
. . .
Internal bus
SFR<2>-1 SFR<2>-2 SFR<2>-3 SFR<1>-1 SFR<1>-2 SFR<1>-3
Internal bus
52
PD784915A, 784916A
(3) Macro service type A When an interrupt occurs, data is transferred from an 8-/16-bit SFR to memory (byte/word) or from memory (byte/ word) to an 8-/16-bit SFR. Data is transferred the number of times set in advance by the macro service counter. This mode can be used to store the result of A/D conversion or for automatic transfer (or reception) by the serial interface. Because transfer data is stored at an address FE00H to FEFFH, if only a small quantity of data is to be transferred, the data can be transferred at high speeds. When the value of the macro service counter is decremented to 0, a vector interrupt occurs.
Data storage buffer (memory) Data n Data n - 1 Data storage buffer (memory) Data n Data n - 1
Data 2 Data 1
Data 2 Data 1
Internal bus
Internal bus
SFR
SFR
(4) Data pattern identification mode (VISS detection mode) This mode of macro service is for detection of the VISS signal and is used in combination with a pulse width detection circuit. When an interrupt occurs, the content of bit 7 of an SFR (usually, TMC3) specified by SFR pointer 1 is shifted into the buffer area. At the same time, the data in the buffer area is compared with the data in the compare area. If the two data coincide, an interrupt request is generated. When the value of the macro service counter is decremented to 0, a vector interrupt occurs. It can be specified by option that the value of an SFR (usually, CPT30) specified by SFR pointer 2 be multiplied by a coefficient and the result of this multiplication be stored to an SFR (usually, CR30) specified by SFR pointer 3 (this operation is to automatically update an identification threshold value when the tape speed fluctuates).
Buffer area (memory) Compare area (memory)
Coefficient (memory)
CPT30 TM3
Coincidence
Multiplier
CR30
CTL F/F (bit 7 of TMC3) Vector interrupt
53
PD784915A, 784916A
4.1.4 Application example of macro service (1) Automatic transfer/reception of serial interface Automatic transfer/reception of 3-byte data by serial interface channel 1 Setting of macro service register: compound data transfer mode (exchange mode)
7 0
FE50H
Higher address
Macro service counter (MSC = 2) Memory pointer H (= FD) Macro service channel Memory pointer L (= 50) ddccbbaa (= 01000100B) SFR pointer <2> (SFRP2 = 85H) SFR pointer <4> (SFRP4 = 85H)
Channel pointer (= 50H) Macro service control word Mode register (= 10110011B) FE2EH Lower address
(Before transfer) (Exchange 2)
SI1
Transmit data 3 FD52H SIO1 (FF85H) <3> Transmit data 2 FD51H <2> (Exchange 1) (Transmit data 1) FD50H <1> Transfer is started by writing transmit data 1 to SIO1 by software.
SO1
(After transfer) Receive data 2 FD51H
Receive data 1 FD50H (Receive data 3 is the data of SIO1.)
54
PD784915A, 784916A
(2) Reception operation of serial interface Transfer of receive data by serial interface channel 1 (16 bytes) Setting of macro service mode register: macro service type A (1-byte transfer from SFR to memory)
Internal RAM FE7FH MSC 0FH SFR pointer 85H Setting of number of transfers Lower 8 bits of address of SIO1 register
Channel pointer (= 7FH) FE2EH Mode register (= 00010001B) Starts macro service when INTCSI1 occurs
SI1
SIO1 (FF85H)
55
PD784915A, 784916A
(3) VISS detection operation Setting of macro service mode register: data pattern identification mode (with multiplication, 8-byte comparison)
CPT30 Higher address FE50H Macro service counter (MSC = FFH) SFR pointer 2 (SFRP2 = 56H) Coefficient (6EH: 43%) SFR pointer 3 (SFRP3 = 5CH) SFR pointer 1 (SFRP1 = 3BH) Buffer size specification register (64 bits: 8H) 1 8 bytes 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit 7 0 TMC3 Multiplier CR30 TM3
0
0
0
0
0
0
0
0
1050H 8 bytes
Compare area pointer (high): 10H Compare area pointer (low): 50H Coincidence (vector interrupt) Channel pointer (= 50H) FE0CH Mode register (= 00010100B) (CTL signal input edge detection interrupt) Lower address
56
PD784915A, 784916A
4.2 Standby Function The standby function serves to reduce the power dissipation of the chip and is used in the following modes: Mode HALT mode STOP mode Low power dissipation mode Low power dissipation HALT mode Function Stops operating clock of CPU. Reduces average power dissipation when used in combination with normal mode for intermittent operation Stops oscillator. Stops all internal operations of chip to minimize current dissipation to leakage current only Stops main system clock with subsystem clock used as system clock. CPU can operate with subsystem clock to reduce power dissipation Standby function in low power dissipation mode. Stops operating clock of CPU. Reduces power dissipation of overall system These modes are programmable. The macro service can be started in the HALT mode. Figure 4-4. Status Transition of Standby Function
Low power dissipation mode (subsystem clock operation)
st ue
Sets low power dissipation mode Restores normal operation
Ma
Normal operation
En En
cro fo
do
se
rvi
ode
Tm
E
put
f os nd o
req
cil at
ion
iliz stab
pe ation
riod
Inter RES
do
fm
ne ro
ce
ac
pro se
req ssi
ce
ue
st
rvi
ng
Macro service
Sets HAL
ce
rupt
pt
ET in
HAL
T in
rru
RE
P2
pu
Set
r dis
req ce rvi cro se Ma En do fo ne pro
I in
INT
owe
NM
W,
wp
INT
s lo
Low power dissipation HALT mode (standby)
Set
STOP mode (standby)
HALT mode (standby)
Unmasked interrupt request
Notes 1. NMI input means starting NMI by NMI pin input, watch interrupt, or key interrupt input. 2. Unmasked interrupt request
ce
ss
ing
Waits for stabilization of oscillation
NM I in
No
1
P
T
TO
requ
t Note
inte
tion
SE
put
sipa
sS
ue
2
st
est
Note
pu
te 1
t
57
PD784915A, 784916A
Figure 4-5. Relations among NMI, Watch Interrupt, and Key Interrupt When STOP Mode Is Released
INTM0.0 Standby control block NMI
Selector
Latch Clear Interrupt control block
INTP1 INTP2 KEY0 KEY1 KEY2 KEY3 KEY4 Cleared when "0" is written to KEYC.7 Mask KEYC.6 Mask KEYC.5 Mask KEYC.4 SQ R WM.6 Cleared when "0" is written to KEYC.0 KEYC.0 SQ R KEYC.7
Selector
Watch timer INTW (OVF) Divides INTW by 128 (HW0L.7)
Mask WM.3
58
peripheral circuits. Figure 4-6 shows the configuration of this circuit.
4.3 Clock Generator Circuit
Figure 4-6. Block Diagram of Clock Generator Circuit
The clock generator circuit generates and controls the internal system clock (CLK) to be supplied to the CPU and
PD784916A
X1
Main system fXX clock oscillation circuit
CC.7 Oscillation Stabilization Timer
Selector
STBC.4, 5 STBC.6
Selector
Low-frequency oscillation mode Normal mode 1/2
1/2
1/2
1/2
fXX/16 (fXX/8)Note 1 fXX/8 (fXX/4)Note 1 fXX/4 (fXX/2)Note 1 fXX/2 (fXX)Note 1
X2 16 MHz or 8 MHz
Selector
Oscillation stop From standby control block
fCLK
CPU Peripheral hardware operation clockNote 2
XT1
XT2 32.768 kHz
Subsystem clock oscillator circuit
fXT
Watch timer
Hardware watch function Watch interrupt
Oscillation stop STBC.7
Note
The peripheral hardware units that can operate with the subsystem clock have some restrictions. For details, refer to 14.6 Low Power Dissipation Mode in PD784915 Subseries User's Manual.
PD784915A, 784916A
59
PD784915A, 784916A
4.4 Reset Function When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset status). During the reset period, oscillation of the system clock is unconditionally stopped, so that the current dissipation of the overall system can be reduced. When the RESET pin goes high, the reset status is cleared. After the count time of the oscillation stabilization timer (32.8 ms at 16 MHz or 65.6 ms at 8 MHz) has elapsed, the contents of the reset vector table are set to the program counter (PC), and execution branches to the address set to the PC, and the program is executed starting from the branch destination address. Therefore, execution can be reset and started from any address. Figure 4-7. Oscillation of Main System Clock during Reset Period
Main system clock oscillation circuit During reset, oscillation is unconditionally stopped. fCLT
RESET input
Oscillation stabilization timer count time
The RESET pin is provided with an analog delay noise rejecter circuit to prevent malfunctioning due to noise. Figure 4-8. Accepting Reset Signal
Oscillation Analog stabilization delay time
Analog delay
Analog delay
RESET input
Internal reset signal
Internal clock
60
PD784915A, 784916A
5. INSTRUCTION SETS
(1) 8-bit instructions (( ): combination realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA
2nd Operand # byte A r r' 1st Operand A (MOV) ADDNote 1 (MOV) (XCH) (ADD)Note 1 r MOV ADDNote 1 (MOV) (XCH) (ADD)Note 1 (MOV)Note 6 (ADD)Note 1 MOV XCH (ADD)Note 1 MOV XCH ADDNote 1 (MOV)Note 6 (XCH)Note 6 MOV (XCH) (MOV) (XCH) ADDNote 1 MOV XCH saddr saddr' sfr !addr16 !!addr24 mem [saddrp] r3 PSWL [WHL+] [WHL-] n None
Note 2
[%saddrg] PSWH MOV XCH ADDNote 1 MOV (MOV) (XCH) (ADD)Note 1 (MOV) (XCH) (ADD)Note 1 RORNote 3 MULU DIVUW INC DEC
(ADD)Notes 1,6 (ADD)Note 1 MOV XCH ADDNote 1 MOV XCH ADDNote 1
saddr
MOV ADDNote 1
MOV ADDNote 1
MOV XCH ADDNote 1
INC DEC DBNZ PUSH POP CHKL CHKLA
sfr
MOV ADDNote 1
MOV (ADD)Note 1
MOV ADDNote 1
!addr16 !!addr24 mem [saddrp] [%saddrg] mem3
MOV
(MOV) ADDNote 1 MOV ADDNote 1
MOV
ROR4 ROL4
r3 PSWL PSWH B, C STBC, WDM [TDE+]
MOV
MOV
DBNZ MOV (MOV) MOVBKNote 5 (ADD)Note 1 MOVMNote 4 MOVBKNote 5
[TDE-]
(MOV) (ADD)Note 1 MOVMNote 4
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. Either the second operand is not used, or the second operation is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short.
61
PD784915A, 784916A
(2) 16-bit instructions (( ): combination realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
2nd Operand # word AX rp rp' 1st Operand AX (MOVM) ADDWNote 1 (MOVW) (XCHW) (ADDW)Note 1 rp MOVW ADDWNote 1 (MOVW) (XCHW) (ADDW)Note 1 saddrp MOVW ADDWNote 1 (MOVW)Note 3 (ADDW)Note 1 (MOVW) (XCHW) (ADDW)Note 1 MOVW XCHW ADDWNote 1 MOVW ADDWNote 1 (MOVW)Note 3 (XCHW)Note 3 MOVW (XCHW) saddrp saddrp' sfrp !addr16 !!addr24 mem [saddrp] [%saddrg] (MOVW) MOVW XCHW XCHW (MOVW) (XCHW) MULWNote 4 INCW DECW INCW DECW [WHL+] byte n None
Note 2
(ADDW)Notes 1, 3 (ADDW)Note 1 MOVW XCHW ADDWNote 1 MOVW XCHW ADDWNote 1 MOVW XCHW ADDWNote 1 MOVW SHRW SHLW
sfrp
MOVW ADDWNote 1
MOVW (ADDW)Note 1 (MOVW)
MOVW ADDWNote 1 MOVW MOVTBLW
PUSH POP
!addr16 !!addr24 mem [saddrp] [%saddrg] PSW
MOVW
MOVW
PUSH POP
SP
ADDWG SUBWG
post
PUSH POP PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes 1. SUBW and CMPW are the same as ADDW. 2. Either the second operand is not used, or the second operation is not an operand address. 3. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short. 4. MULUW and DIVUX are the same as MULW.
62
PD784915A, 784916A
(3) 24-bit instructions (( ): combination realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP
2nd Operand # imm24 WHL rg rg' 1st Operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP NoneNote
Note
Either the second operand is not used, or the second operation is not an operand address.
(4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET 2nd Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit iaddr16.bit 1st Operand CY !addr24.bit MOV1 AND1 OR1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit Note Either the second operand is not used, or the second operation is not an operand address. MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NOT1 SET1 CLR1 NoneNote
63
PD784915A, 784916A
(5) Call/return and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Operand of instruction address Basic instruction BCNote CALL BR BR CALL BR RETCS RETCSB Compound instruction BF BT BTCLR BFSET DBNZ CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLT BRKCS BRK RET RETI RETB $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None
Note
BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC.
(6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
64
PD784915A, 784916A
6. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD AVDD1 AVDD2 AVSS1 AVSS2 Input voltage Analog input voltage (ANI0-ANI11) Output voltage Low-level output current High-level output current Operating ambient temperature Storage temperature Caution VO IOL IOH TA Tstg Pin 1 Total of all pins Pin 1 Total of all pins VI VIAN VDD AVDD2 VDD < AVDD2 Condition | VDD - AVDD1 | 0.5 V |VDD - AVDD2 | 0.5 V |AVDD1 - AVDD2 | 0.5 V Ratings -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 -0.5 to AVDD2 + 0.5 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 15 100 -10 -50 -10 to +70 -65 to +150 Unit V V V V V V V V V mA mA mA mA C C
If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings therefore specify the values exceeding which the product may be physically damaged. Never exceed these values when using the product.
Operating Conditions Clock Frequency 4 MHz fXX 16 MHz 32 kHz fXT 35 kHz Operating Temperature (TA) -10 to +70C Operating Conditions All functions CPU function only Subclock operation (CPU, watch, and port functions only) Supply Voltage (VDD) +4.5 to +5.5 V +4.0 to +5.5 V +2.7 to +5.5 V
65
PD784915A, 784916A
Oscillator Characteristics (main clock) (TA = -10 to +70C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V) Oscillator Crystal oscillator
X1 X2 VSS
Recommended Circuit
Parameter Oscillation frequency (fXX)
MIN. 4
MAX. Unit 16 MHz
C1
C2
Oscillator Characteristics (subclock) (TA = -10 to +70C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V) Oscillator Crystal oscillator
X1 X2 VSS
Recommended Circuit
Parameter Oscillation frequency (fXT)
MIN. 32
MAX. Unit 35 kHz
C1
C2
Caution
When using the main system clock and subsystem clock oscillation circuits, wire the portion enclosed by the broken line in the above figures as follows to avoid the adverse influence of wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring in the neighborhood of a signal line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit to the same potential as VSS. Do not ground the capacitor to a ground pattern to which a high current flows. * Do not extract signals from the oscillation circuit. Exercise particular care in using the subsystem clock oscillation circuit because the amplification factor of this circuit is kept low to reduce the power dissipation.
66
PD784915A, 784916A
DC Characteristics (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Low-level input voltage Symbol VIL1 VIL2 VIL3 High-level input voltage VIH1 VIH2 VIH3 Low-level output voltage VOL1 VOL2 VOL3 High-level output voltage VOH1 VOH2 Input leakage current Output leakage current VDD supply current ILI ILO IDD1 Conditions Pins other than those listed in Notes 1 and 4 below Pins listed in Notes 1 and 4 below X1, X2 Pins other than those listed in Note 1 below Pins listed in Note 1 below X1, X2 IOL = 5.0 mA (pins in Note 2) IOL = 2.0 mA IOL = 100 A IOH = -1.0 mA IOH = -100 A 0 VI VDD 0 VO VDD Operation mode fXX = 16 MHz fXX = 8 MHz (low-frequency oscillation mode) Internally, 8-MHz main system clock operation fXT = 32.768 kHz Subclock operation (CPU, watch, port) VDD = 2.7 V IDD2 HALT mode fXX = 16 MHz fXX = 8 MHz (low-frequency oscillation mode) Internally, 8-MHz main clock operation fXT = 32.768 MHz Subclock operation (CPU, watch, port) VDD = 2.7 V Data hold voltage Data hold current Note 3 VDDDR IDDDR STOP mode STOP mode Subclock oscillates VDDDR = 5.0 V STOP mode Subclock oscillates VDDDR = 2.7 V STOP mode Subclock stops VDDDR = 2.5 V Pull-up resistor RL VI = 0 V 25 55 110 k 0.2 7.0 2.5 10 2.5 18 50 V 25 50 10 25 mA 50 80 30 VDD - 1.0 VDD - 0.4 10 10 50 MIN. 0 0 0 0.7 VDD 0.8 VDD VDD - 0.5 TYP. MAX. 0.3 VDD 0.2 VDD 0.4 VDD VDD VDD 0.6 0.45 0.25 Unit V V V V V V V V V V V
A A
mA
A
A
A A A
Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0P95/KEY4 2. P46, P47 3. In the STOP mode in which the subclock oscillation is stopped, disconnect the feedback resistor, and connect the XT1 pin to VDD. 4. P40 to P47, P50 to P57
67
PD784915A, 784916A
AC Characteristics CPU and peripheral circuit operation clock (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter CPU operation clock cycle time Symbol tCLK fXX = 16 MHz Condition VDD = AVDD = 4.0 to 5.5 V CPU Function only fXX = 16 MHz fXX = 8 MHz low-frequency oscillation mode (Bit 7 of CC = 1) Peripheral operation clock cycle time tCLK1 fXX = 16 MHz fXX = 8MHz low-frequency oscillation mode (Bit 7 of CC = 1) 125 ns TYP. 125 Unit ns
Serial interface (1) SIOn: n = 1 or 2 (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Input Output Condition External clock fCLK1/8 fCLK1/16 fCLK1/32 fCLK1/64 fCLK1/128 fCLK1/256 Serial clock high- and low-level widths SIn setup time (vs. SCKn ) SIn hold time (vs. SCKn ) SOn output delay time (vs. SCKn ) tWSKH tWSKL tSSSK tHSSK tDSSK Input Output External clock Internal clock MIN. 1.0 1.0 2.0 4.0 8.0 16 32 420 tCYSK/2 - 50 100 400 0 300 MAX. Unit
s s s s s s s
ns ns ns ns ns
Remarks 1. fCLK1: operating clock of peripheral circuit (8 MHz) 2. n = 1 or 2 (2) SIO2 only (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter SCK2(8) STBR Strobe high-level width BUSY setup time (vs. BUSY detection timing) BUSY hold time (vs. BUSY detection timing) BUSY inactive SCK2(1) tLBUSY tCYSK + tWSKH tHBUSY 100 ns Symbol tDSTRB tWSTRB tSBUSY Condition MIN. tWSKH tCYSK - 30 100 MAX. tCYSK tCYSK + 30 ns ns Unit
Remarks 1. The value in ( ) following SCK2 indicates the number of SCK2. 2. BUSY is detected after the time (n+2) x tCYSK (n = 0, 1, and so on) has elapsed relative to SCK2 (8) . 3. BUSY inactive SCK2 (1) is the value when data write to SIO2 has been completed.
68
PD784915A, 784916A
Other operations (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Timer input signal low-level width Symbol tWCTL Condition When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input Timer input signal high-level width tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input Timer input signal valid edge input cycle CSYNCIN low-level width tPERIN tWCR1L When DFGIN, CFGIN, or DPGIN is input When digital noise elimination circuit is not used When digital noise elimination circuit is used (Bit 4 of INTM2 = 0) When digital noise elimination circuit is used (Bit 4 of INTM2 = 1) CSYNCIN high-level width tWCR1H When digital noise elimination circuit is not used When digital noise elimination circuit is used (Bit 4 of INTM2 = 0) When digital noise elimination circuit is used (Bit 4 of INTM2 = 1) Digital noise elimination circuit Passed pulse width Eliminated pulse width tWSEP Bit 4 of INTM2 = 0 Bit 4 of INTM2 = 1 Bit 4 of INTM2 = 0 Bit 4 of INTM2 = 1 NMI low-level width NMI high-level width INTP0, INTP3 low-level widths INTP0, INTP3 high-level widths INTP1, KEY0-KEY4 low-level widths tWNIL tWNIH tWIPL0 tWIPH0 tWIPL1 Mode other than STOP mode In STOP mode, for releasing STOP mode INTP1, KEY0-KEY4 high-level widths tWIPH1 Mode other than STOP mode In STOP mode, for releasing STOP mode INTP2 low-level width tWIPL2 In normal mode, with main clock Normal mode, with subclock Sampling = fCLK Sampling = fCLK/128 Sampling = fCLK Sampling = fCLK/128 VDD = AVDD = 2.7 to 5.5 V VDD = AVDD = 2.7 to 5.5 V 108tCLK1 180tCLK1 10 10 2tCLK1 2tCLK1 2tCLK1 10 2tCLK1 10 2tCLK1 32Note 61 7.9Note 10 2tCLK1 32Note 61 7.9Note 10 10 104tCLK1 176tCLK1 ns ns ns ns 180tCLK1 ns 8tCLK1 108tCLK1 ns ns 180tCLK1 ns 2 8tCLK1 108tCLK1 tCLK1 ns MIN. tCLK1 MAX. Unit ns
s
ns ns
s s
ns ns ns
s
ns
s
ns
s s
ms
In STOP mode, for releasing STOP mode INTP2 high-level width tWIPH2 In normal mode, with main clock Normal mode, with subclock Sampling = fCLK Sampling = fCLK/128 Sampling = fCLK Sampling = fCLK/128
s
ns
s s
ms
In STOP mode, for releasing STOP mode RESET low-level width tWRSL
s s
Note
If a high or low level is successively input two times during the sampling period, a high or low level is detected.
Remark tCKL1: operating clock cycle time of peripheral circuit (125 ns)
69
PD784915A, 784916A
Clock output operation (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter CLO cycle time CLO low-level width CLO high-level width CLO rise time CLO fall time Symbol tCYCL tCLL tCLH tCLR tCLF tCYCL/2 50 tCYCL/2 50 Condition MIN. 250 75 75 MAX. 2000 1050 1050 50 50 Unit ns ns ns ns ns
Data hold characteristics (TA = -10 to +70C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Low-level input voltage High-level input voltage Symbol VIL VIH Condition Special pins (pins in Note) MIN. 0 0.9 VDDDR TYP. MAX. 0.1 VDDDR VDDDR Unit V V
Note
RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN P91/KEY0-P95/ KEY4
Watch function (TA = -10 to +70C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Subclock oscillation hold voltage Hardware watch function operating voltage Symbol VDDXT VDDW Condition MIN. 2.7 2.7 MAX. Unit V V
Subclock oscillation stop detection flag (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Oscillation stop detection width Symbol tOSCF Condition MIN. 45 MAX. Unit
s
A/D converter characteristics (TA = -10 to +70C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error Quantization error Conversion time tCONV Bit 4 of ADM = 0 Bit 4 of ADM = 1 Sampling time tSAMP Bit 4 of ADM = 0 Bit 4 of ADM = 1 Analog input voltage Analog input impedance AVREF current VIAN ZAN AIREF 160tCLK1 80tCLK1 32tCLK1 16tCLK1 0 1000 0.4 1.2 AVREF AVREF = VDD Symbol Condition MIN. 8 2.0 1/2 TYP. MAX. Unit bit % LSB
s s s s
V M mA
VREF amplifier (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Reference voltage Charge current Symbol VREF ICHG Sets AMPM0.0 to 1 (pins in Note) Condition MIN. 2.35 300 TYP. 2.50 MAX. 2.65 Unit V
A
Note
RECCTL+, RECCTL-, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN
70
PD784915A, 784916A
CTL amplifier (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter CTL+, - input resistance Feedback resistance Bias resistance Minimum voltage gain Maximum voltage gain Gain selecting step In-phase elimination ratio Symbol RICTL RFCTL RBCTL GCTLMIN GCTLMAX SGAIN CMR DC, voltage gain: 20 dB Condition MIN. 2 20 20 17 71 TYP. 5 50 50 20 75 1.77 30 VREF + 0.47 VREF + 0.50 VREF + 0.53 VREF + 0.27 VREF + 0.30 VREF + 0.33 VREF - 0.53 VREF - 0.50 VREF - 0.47 VREF - 0.33 VREF - 0.30 VREF - 0.27 150 200 250 MAX. 10 100 100 22 Unit k k k dB dB dB dB V V V V mV V V V V
High comparator set voltage of waveform shaping VPBCTLHS High comparator reset voltage of waveform shaping VPBCTLHR Low comparator set voltage of waveform shaping VPBCTLLS
Low comparator reset voltage of waveform shaping VPBCTLLR Waveform shaping comparator Schmit width High comparator voltage of CTL flag S Low comparator voltage of CLT flag S High comparator voltage of CTL flag L Low comparator voltage of CTL flag L VPBSH VFSH VFSL VFLH VFLL
VREF + 1.00 VREF + 1.05 VREF + 1.10 VREF - 1.10 VREF - 1.05 VREF - 1.00 VREF + 1.40 VREF + 1.45 VREF + 1.50 VREF - 1.50 VREF - 1.45 VREF - 1.40
CFG amplifier (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Voltage gain 1 Voltage gain 2 CFGAMPO High-level output current CFGAMPO Low-level output current High comparator voltage Low comparator voltage Duty accuracy Symbol GCFG1 GCFG2 IOHCFG IOLCFG VCFGH VCFGL PDUTY Note Condition fi = 2 kHz, open loop fi = 30 kHz, open loop DC DC MIN. 50 34 -1 0.1 VREF + 0.09 VREF + 0.12 VREF + 0.15 VREF - 0.15 VREF - 0.12 VREF - 0.09 49.7 50.0 50.3 TYP. MAX. Unit dB dB mA mA V V %
Note
The conditions include the following circuit and input signal. Input signal : Sine wave input (5 mVp-p) fi = 1 kHz Voltage gain: 50 dB
1 k -+ 22 F 330 k CFGIN
PD784916A
CFGAMPO 0.01 F
CFGCPIN
71
PD784915A, 784916A
DFG amplifier (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Voltage gain Feedback resistance Input protection resistance High comparator voltage Low comparator voltage Symbol GDFG RFDFG RIDFG VDFGH VDFGL Condition fi = 900 Hz, open loop MIN. 50 160 400 150 VREF + 0.07 VREF + 0.10 VREF + 0.14 VREF - 0.14 VREF - 0.10 VREF - 0.07 640 TYP. MAX. Unit dB k V V
Caution
Set the input resistance connected to the DFGIN pin to 16 k or below. Connecting a resistor exceeding that value may cause the DFG amp to oscillate.
DPG comparator (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZIDPG VDPGH VDPGL Condition MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF + 0.02 VREF + 0.05 VREF + 0.08 VREF - 0.08 VREF - 0.05 VREF - 0.02
Ternary separation circuit (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZIPFG VPFGH VPFGL Condition MIN. 20 TYP. 50 MAX. 100 VREF + 0.9 VREF - 1.0 Unit k V V
VREF + 0.5 VREF + 0.7 VREF - 1.4 VREF - 1.2
CSYNC comparator (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZICSYN VCSYNH VCSYNL Condition MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF + 0.07 VREF + 0.10 VREF + 0.13 VREF - 0.13 VREF - 0.10 VREF - 0.07
Reel FG comparator (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZIRLFG VRLFGH VRLFGL Condition MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF + 0.02 VREF + 0.05 VREF + 0.08 VREF - 0.08 VREF - 0.05 VREF - 0.02
RECCTL driver (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter RECCTL+, - high-level output voltage RECCTL+, - low-level output voltage CTLDLY internal resistance CTLDLY charge current CTLDLY discharge current Symbol Condition MIN. VDD - 0.8 0.8 40 Use of internal resistor -3 -3 70 140 TYP. MAX. Unit V V k mA mA
VOHREC IOH = -4 mA VOLREC RCTL IOHCTL IOLCTL IOL = 4 mA
72
PD784915A, 784916A
Timing waveform AC timing test point
0.8 VDD or 2.2 V Test points 0.8 V 0.8 V 0.8 VDD or 2.2 V
Serial transfer timing (SIOn: n = 1 or 2)
tWSKL SCKn tCYSK SIn tSSSK tHSSK Input data tWSKH
tDSSK SOn Output data
73
PD784915A, 784916A
Serial transfer timing (SIO2 only) No busy processing
tWSKL SCK2 7 tCYSK BUSY Active high tOSTRB STRB Busy invalid tWSTRB tWSKH 8 9 10 1 2
Continuation of busy processing
tWSKL SCK2 7 tCYSK BUSY tWSKH 8 9 tSBUSY 10 10+n tSBUSY
Active high tDSTRB tWSTRB
STRB
End of busy processing
tWSKL SCK2 7 tCYSK BUSY tWSKH 8 9 10+n tHBUSY 11+n tLBUSY 1
Active high
Caution
When an external clock is selected as the serial clock, do not use the busy control or strobe control.
74
PD784915A, 784916A
Super timer unit input timing
tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input 0.8 VDD 0.8 V tWCTL
tWCR1H When CSYNCIN logic level is input 0.8 VDD 0.8 V
tWCR1L
Interrupt input timing
tWNIH NMI 0.8 VDD 0.8 V tWNIL
tWIPH0 INTP0, INTP3 0.8 VDD 0.8 V
tWIPL0
tWIPH1 0.8 VDD 0.8 V
tWIPL1
INTP1, KEY0-KEY4
tWIPH2 0.8 VDD INTP2 0.8 V
tWIPL2
Reset input timing
tWRSL
RESET 0.8 V
75
PD784915A, 784916A
Clock output timing
tCLH CLO 0.8 VDD 0.8 V tCLR tCLF tCLL tCYCL
76
PD784915A, 784916A
7. PACKAGE DRAWING
100 PIN PLASTIC QFP (14 x 20)
A B
80 81
51 50
detail of lead end
C
D
S
100 1
31 30
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I Remark External Dimensions of the ES version are the same as those of the mass-produced version. J K L M N P Q S
L P100GF-65-3BA1-2 MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 0.8 0.6 0.30 0.10 0.15 0.65 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
M
55
Q
77
PD784915A, 784916A
8. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the PD784915A and 784916A. For details of the recommended soldering conditions, refer to the NEC document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 18-1. Soldering Conditions for Surface-Mount Type
PD784915AGF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD784916AGF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm)
Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1
Soldering Method Infrared reflow VPS Wave soldering
Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: 3 max. Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above), Number of times: 3 max. Solder bath temperature: 260C max. Duration: 10 sec. max. Number of times: 1 Preliminary heat temperature: 120C max. (Package surface temperature)
Partial heating
Pin temperature: 300C max., Duration: 3 sec. max. (per device side)
-
Caution
Using more than one soldering method should be avoided (except in the case of partial heating).
78
PD784915A, 784916A
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD784916A. Language Processing Software RA78K4Note 1 CC78K4Note 1 CC78K4-LNote 1 PROM Writing Tools PG-1500 PA-78P4916GF PG-1500 controllerNote 2 Debugging Tools IE-784000-R IE-784000-R-BK IE-784000-R-EM IE-784915-R-EM1 IE-78000-R-SV3 IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B EP-784915GF-R EV-9200GF-100 SM78K4Note 3 ID78K4Note 3 DF784915Note 4 Real-time OS RX78K/IVNote 4 MX78K4Note 2 78K/IV Series common real-time OS 78K/IV Series common OS 78K/IV Series common in-circuit emulator 78K/IV Series common break board 78K/IV Series common emulation board PROM programmer PROM programmer adapter connected to PG-1500 PG-1500 control program 78K/IV Series common assembler package 78K/IV Series common C compiler package 78K/IV Series common C compiler library source file
PD784915 Subseries evaluation emulation board
Interface adapter and cable when an EWS is used as the host machine Interface adapter when PC-9800 Series (except notebook PC) is used as the host machine Interface adapter and cable when PC-9800 Series notebook PC is used as the host machine Interface adapter when IBM PC/ATTM is used as the host machine
PD784915 Subseries common emulation probe
Conversion socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA) 78K/IV series common system simulator IE-784000-R integrated debugger
PD784915 Subseries common device file
79
PD784915A, 784916A
Notes 1. * PC-9800 Series (MS-DOSTM) based * IBM PC/AT and compatibles (PC DOSTM, WindowsTM, MS-DOS, IBM DOSTM) based * HP9000 Series 700TM (HP-UXTM) based * SPARCstationTM (SunOSTM) based * NEWSTM (NEWS-OSTM) based 2. * PC-9800 Series (MS-DOS) based * IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, IBM DOS) based 3. * PC-9800 Series (MS-DOS + Windows) based * IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, IBM DOS) based * HP9000 Series 700 (HP-UX) based * SPARCstation (SunOS) based 4. * PC-9800 Series (MS-DOS) based * IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, IBM DOS) based * HP9000 Series 700 (HP-UX) based * SPARCstation (SunOS) based Remark The RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784915.
80
PD784915A, 784916A
APPENDIX B. RELATED DOCUMENTS
Documents related to devices Document Number Japanese U10444J U11044J U11022J U11045J U11361J U10976J U10905J U10594J U10595J U10095J English U10444E U11044E This document U11045E U11361E - U10905E - - U10095E
Document Name
PD784915 Subseries User's manual - Hardware PD784915 Data Sheet PD784915A, 784916A Data Sheet PD78P4916 Data Sheet PD784915 Subseries Appllication Note PD784915 Subseries Special function register table
78K/IV Series User's manual - Instruction 78K/IV Series Instruction table 78K/IV Series Instruction set 78K/IV Series Application note - Software fundamental Documents related to development tools (user's manual)
Document Name RA78K Series Assembler package RA78K Series Structured assembler preprocessor CC78K4 Series CC78K Series Library source file PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) based PG-1500 Controller IBM PC Series (PC DOS) based IE-784000-R IE-784915-R-EMI SM78K4 System Simulator Windows SM78K Series System Simulator
TM
Document Number Japanese Language Operation Language Operation U11162J U11334J U11743J EEU-961 EEU-960 U12322J U11940J EEU-704 EEU-5008 EEU-5004 U10931J English U11162E U11334E U11743E - - - EEU-1335 EEU-1291 U10540E EEU-1534 - U10093E U10092E
based
Reference open interface specifications
U10093J
External parts user U10092J
ID78K4 Integrated debugger - PC-9801, 9821 Series (Windows) based Reference ID78K4 Integrated debugger - HP9000 Series 700 (HP-UX) based Reference
U10440J U11960J
U10440E -
81
PD784915A, 784916A
Documents related to embedded software (user's manual) Document Number Japanese Basics Installation Debugger 78K/IV Series OS MX78K4 Caution U10603J U10604J U10364J English U10603E U10604E - -
Document Name RX78K/IV Real-time OS
Fundamental U11779J
The documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Other related documents Document Number Japanese C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E - MEI-1202 - English
Document Name IC package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer Product Series Guide Caution
The documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
82
PD784915A, 784916A
[MEMO]
83
PD784915A, 784916A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
84
PD784915A, 784916A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
85
PD784915A, 784916A
The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such.
FIP is a registered trademark of NEC Corporation. MS-DOS and Windows are either trademarks or registered trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC-DOS are trademarks of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPRC International, Inc. SunOS ia a trademark of Sun Microsystems, Inc. NEWS and NEW-OS are trademarks of Sony Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-in's.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

▲Up To Search▲

Price & Availability of UPD784916AGF

	To Download UPD784916AGF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .